“DDR2 Design Analysis”

On Ramp to High Speed Electronic Design


Presenter: Craig Arno


Abstract:

Let’s explore a working high speed DDR2 reference design and analyze the performance impact of a gap in a copper plane between an ARM processor and its DDR2 RAM subsystem. The result of this analysis is to determine if the system can operate reliably with this gap. Such a gap can be intentional, or an oversight.

Starting with manual analysis in the form of a simple model, equations, and calculation, then perform further simulation using SPICE, then explore IBIS modeling using Altium Designer. Finally, compare results.

The intent is to demonstrate for implementers and designers some basic high speed design principles. Understanding basic HS design rules can potentially save a project millions of dollars caused by schedule delay and missed market opportunity.

Speaker Biography:

Craig Arno has a degree in Electrical Engineering from the University of Washington, and worked as an engineer in the Medical and Avionics industries for 35 years designing both hardware and software. Craig worked as a consulting engineer for 25 years at companies like; Siemens Medical Systems, Motorola, Microsoft, Honeywell, Sagem Avionics, and Physio Control Corporation. Assignments range from hardware engineering lead for design of a high speed 100+ channel ultrasound A/D capture subsystem, to writing FDA controlled product software and algorithms in C and C++. Craig enjoys working with other skilled engineers to solve difficult engineering design challenges where a balance of creativity, discipline, and skill are required.

Date:

September 20, 2017
6:00pm - 8:00pm

Registration:

Eventbrite - IPC Designers Council - Cascade Chapter Meeting - September

Location:

Lake Washington Institute of Technology - Kirkland Campus
Room A102
11605 132nd Ave NE
Kirkland, WA 98034


Park in the south lot off of 132nd Ave NE. Room A102 is located in the south-east corner of the building, on the 1st floor.