“DFM & DFT, Part 2 – The Risk / Cost Factor Defined & Quantified!”


Presenter: Cherie Litson

June 13th, 2018, 11:30am – 1:30pm

 

Abstract:

Last time, we learned how planning early could help us pay less. That’s all well & good, but how do I know
when I’ve made the best plan? How many risks can I take before everything starts to become very expensive?

At this meeting, you’ll get some tools to help you define your design!

 

Speaker Biography:

Currently the principal in Litson1 Consulting, my background includes P & L responsibility for corporate design teams. I have developed and presented targeted educational programs for engineering staff, non-technical personnel, and overseas clients. I have managed the development of Component Database systems that integrated purchasing, engineering, design, and manufacturing.

I am qualified as an IPC Certified Master Interconnect Design Instructor at the basic (CID) and advanced level (CID+). I have served as a technical instructor for IPC since 2003. Through the training centers of EPTAC & IPC directly, I have certified over 400 designers, engineers, and manufacturing personnel in PCB design principles and standards.

Over 30 years of electronics industry experience in the medical, aviation, and commercial sectors has given me a broad perspective. My knowledge, training, and experience are an asset in developing PCB designs with electrical, mechanical, & fiscal integrity. My expertise in the field of PCB design, Electrical Engineering, Project Management, and Manufacturing Services, produce cost efficient products for my clients.

 

Registration:

Eventbrite - IPC Designers Council - Cascade Chapter Meeting - November

 

Location:

Lake Washington Institute of Technology – Kirkland Campus
Room A102
11605 132nd Ave NE
Kirkland, WA 98034 

Park in the south lot off of 132nd Ave NE. Room A102 is located in the south-east corner of the building, on the 1st floor.

 

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